Three-Phase Phase-Locked Loop Algorithms Based on Sliding Modes

Grid-voltage Synchronization Algorithms Based on Phase-locked Loop and Frequency-locked Loop for Power Converters

High Speed Delay-Locked Loop for Multiple Clock Phase Generation

In this paper, a high speed delay-locked loop (DLL) architecture ispresented which can be employed in high frequency applications. In order to design the new architecture, a new mixed structure is presented for phase detector (PD) and charge pump (CP) which canbe triggered by double edges of the input signals. In addition, the blind zone is removed due to the elimination of reset signal. Theref...

An Efficient Phase-Locked Loop for Distorted Three-Phase Systems

This paper proposed an efficient phase-locked loop (PLL) that features zero steady-state error of phase and frequency under voltage sag, phase jump, harmonics, DC offsets and step-and ramp-changed frequency. The PLL includes the sliding Goertzel discrete Fourier transform (SGDFT) filter-based fundamental positive sequence component separator (FPSCS), the synchronousreference-frame PLL (SRF-PLL)...

Phase Locked Loop Circuits

1. Definition. A PLL is a feedback system that includes a VCO, phase detector, and low pass filter within its loop. Its purpose is to force the VCO to replicate and track the frequency and phase at the input when in lock. The PLL is a control system allowing one oscillator to track with another. It is possible to have a phase offset between input and output, but when locked, the frequencies mus...

Photonic phase-locked-loop linear phase demodulator

Design and experimental validation of a simple photonic phase-lockedloop (PPLL) linear phase demodulator employing a novel attenuating counter propagating (ACP) in-loop phase modulator are presented. The ACP in-loop phase modulator is free of propagation delay, allowing stable operation of the PPLL with large gain. Highly linear optical phase demodulation was observed and the measured spurious ...